A pulse-triggered TSPC flip-flop for high-speed low-power VLSI design applications

Author

Jinn-Shyan Wang ; Po-Hui Yang

Author_Institution

Dept. of Electr. Eng., Nat. Chung-Cheng Univ., Chia-Yi

Volume

2

fYear

1998

fDate

31 May-3 Jun 1998

Firstpage

93

Abstract

A new fast low-power flip-flop, called pulse-triggered TSPC flip-flop (PTTFF), is proposed. PTTFF uses a conventional latch structure clocked by a short pulse train, and it indeed acts as a flip-flop. The new flip-flop uses only 5 MOS transistors with only one transistor being clocked. Both the total transistor count and the number of clocked transistors per flip-flop are reduced to save the power consumption of the flip-flop itself and the clocking system. For a pipelined FIR macro, utilizing the proposed PTTFF can save up to 63% of power consumption of the clocking system. PTTFF can also operate very fast. The maximum toggle rate of PTTFF can be as high as 3 GHz if designed in a 0.6 μm CMOS technology

Keywords

CMOS logic circuits; VLSI; clocks; flip-flops; integrated circuit design; pipeline processing; 0.6 micron; 3 GHz; CMOS technology; clocked transistors; high-speed low-power VLSI design; latch structure; pipelined FIR macro; power consumption; pulse train; pulse-triggered TSPC flip-flop; toggle rate; transistor count; true single-phase clocking; CMOS technology; Clocks; Energy consumption; Flip-flops; Frequency; MOSFETs; Parasitic capacitance; Power generation; Very large scale integration; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.706849

Filename

706849