Title :
A 900 MHz, 2.5 mA CMOS frequency synthesizer with an automatic SC tuning loop
Author :
Lin, Tsung-Hsien ; Kaiser, William J.
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Abstract :
A 900 MHz PLL frequency synthesizer implemented in 0.6 μm CMOS technology is developed for WINS (Wireless Integrated Network Sensors) applications. It incorporates an automatic SC discrete-tuning loop to extend the frequency tuning range to 20% while the VCO gain from the CMOS varactor continuous-tuning is kept low at only 20 MHz/V, to minimize the reference spurs. This frequency synthesizer achieves a phase noise of -102 dBc/Hz at 100 kHz offset and reference spurs below -55 dBc. The synthesizer, including an on-chip VCO, dissipates only 2.5 mA from a 3 V supply
Keywords :
CMOS integrated circuits; UHF integrated circuits; circuit tuning; frequency synthesizers; low-power electronics; mixed analogue-digital integrated circuits; phase locked loops; phase noise; switched capacitor networks; voltage-controlled oscillators; 2.5 mA; 3 V; 900 MHz; ASIC; CMOS PLL frequency synthesizer; CMOS varactor continuous-tuning; SC discrete-tuning loop; VCO gain; WINS applications; automatic SC tuning loop; frequency tuning range; onchip VCO; phase noise; reference spurs minimisation; ultra low power operation; wireless integrated network sensors; CMOS technology; Frequency synthesizers; Inductors; Noise measurement; Phase locked loops; Phase noise; Tuning; Varactors; Voltage-controlled oscillators; Wireless sensor networks;
Conference_Titel :
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5809-0
DOI :
10.1109/CICC.2000.852689
