Linearity optimization of a high power Doherty amplifier

Author

Cho, Kyoung-Joon ; Hwang, In-Hong ; Kim, Wan-Jong ; Kim, Jong-Heon ; Stapleton, Shawn P.

fYear

2005

fDate

12-17 June 2005

Abstract

The linearity of a 30 W high power Doherty amplifier is optimized using post-distortion compensation. A balanced high power Doherty amplifier using two push-pull LDMOS FETs is linearized by optimum adjustment of the peaking compensation line, shunt capacitors and gate biases. The optimized Doherty amplifier measured results for a 4-carrier W-CDMA signal, achieved -43 dBc ACLR at a ±5 MHz offset frequency. This is an ACLR improvement of 12.2 dB and 6.5 dB in comparison to the Doherty amplifier before optimization and a class AB amplifier, respectively.

Keywords

MOSFET; circuit optimisation; linearisation techniques; microwave power amplifiers; 30 W; 4-carrier W-CDMA signal; class AB amplifier; gate bias; high power Doherty amplifier; linear power amplifier; linearity optimization; peaking compensation line; post-distortion compensation; push-pull LDMOS FET; shunt capacitors; wideband code division multiple access; Broadband amplifiers; FETs; High power amplifiers; Linearity; Multiaccess communication; Power amplifiers; Power engineering and energy; Predistortion; Radiofrequency amplifiers; Transfer functions;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium Digest, 2005 IEEE MTT-S International

ISSN

01490-645X

Print_ISBN

0-7803-8845-3

Type

conf

DOI

10.1109/MWSYM.2005.1516942

Filename

1516942