DocumentCode
2159533
Title
Effect of technology scaling on digital CMOS logic styles
Author
Allam, Mohamed ; Anis, Mohab ; Elmasry, Mohamed
Author_Institution
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
fYear
2000
fDate
2000
Firstpage
401
Lastpage
408
Abstract
In this paper, the main challenges of technology scaling are reviewed in depth. Five popular logic families, namely, conventional CMOS, CPL, Domino, DCVS and MCML are represented highlighting their advantages and drawbacks. The behavior of each logic style in deep submicron technologies is analyzed and predicted for future generations. To verify the qualitative analysis, simulations were performed on the basic logic gates, full adder and a 16-bit carry look ahead adder. The circuits were implemented in 0.8, 0.6, 0.35 and 0.25 μm CMOS technologies
Keywords
CMOS logic circuits; adders; carry logic; circuit optimisation; logic gates; 0.25 to 0.8 micron; 16 bit; CPL; DCVS; Domino; MCML; basic logic gates; carry look ahead adder; conventional CMOS; deep submicron technologies; digital CMOS logic styles; full adder; technology scaling; Adders; Analytical models; CMOS logic circuits; CMOS technology; Circuit simulation; Integrated circuit technology; Logic devices; Logic gates; Power dissipation; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location
Orlando, FL
Print_ISBN
0-7803-5809-0
Type
conf
DOI
10.1109/CICC.2000.852695
Filename
852695
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