Title :
A noise-tolerant dynamic circuit design technique
Author :
Balamurugan, Ganesh ; Shanbhag, Naresh R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Abstract :
A new circuit technique, referred to as the twin-transistor technique, for increasing the noise immunity of dynamic logic circuits is presented. This technique makes dynamic logic gates more tolerant to noise appearing at the gate inputs. A multiply-accumulate circuit has been designed and fabricated using a 0.35 μm process to verify this technique. Experimental results indicate that the twin-transistor technique provides a significant improvement in the noise immunity of dynamic circuits (>2.4 X) with only a modest increase in power dissipation (15%) and no loss in throughput
Keywords :
CMOS logic circuits; integrated circuit design; integrated circuit noise; logic design; logic gates; 0.35 micron; dynamic circuit design technique; dynamic logic circuits; dynamic logic gates; multiply-accumulate circuit; noise-tolerant circuit design; twin-transistor technique; Circuit noise; Circuit synthesis; Circuit testing; Crosstalk; Delay; Integrated circuit noise; Logic circuits; Noise level; Power dissipation; Threshold voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5809-0
DOI :
10.1109/CICC.2000.852700
