Title :
Analysis of jitter due to power-supply noise in phase-locked loops
Author :
Heydari, Payam ; Pedram, Massoud
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
Phase-locked loops (PLL) in RF and mixed signal VLSI circuits experience supply noise which translates to a timing jitter. In this paper an analysis of the timing jitter due to the noise on the power supply rails is presented. Stochastic models of the power supply noise in VLSI circuits for different values of on-chip decoupling capacitances are presented first. This is followed by calculation of the phase noise of the voltage-controlled oscillator (VCO) in terms of the statistical properties of supply noise. Finally the timing jitter of the PLL is predicted in response to the VCO phase noise. A PLL circuit has been designed in 0.35 μm CMOS process, and our mathematical model was applied to determine the timing jitter. Experimental results prove the accuracy of the predicted model
Keywords :
CMOS integrated circuits; UHF integrated circuits; VLSI; capacitance; integrated circuit noise; mixed analogue-digital integrated circuits; network analysis; phase locked loops; phase noise; stochastic processes; timing jitter; voltage-controlled oscillators; 0.35 micron; CMOS PLL circuit; RF circuits; VCO phase noise; jitter analysis; mathematical model; mixed signal VLSI circuits; onchip decoupling capacitances; phase-locked loops; power supply noise; power supply rails; statistical properties; stochastic models; timing jitter; voltage-controlled oscillator; Circuit noise; Phase locked loops; Phase noise; Power supplies; RF signals; Radio frequency; Rails; Timing jitter; Very large scale integration; Voltage-controlled oscillators;
Conference_Titel :
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5809-0
DOI :
10.1109/CICC.2000.852704
