A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems

This paper deals with the design and implementation of a frame, time and frequency synchronizer for both Hiperlan/2 and IEEE 802.11a WLAN standards. In a packet oriented system, to perform a quick and correct synchronization it is critical to avoid severe bit error rate degradation. So, the design of this subsystem is one of the most challenging tasks to be done in the implementation of a transceiver. In this paper we give practical solutions to the hardware design problems that arise when the synchronization algorithm is turned into a digital circuit. We evaluate the fixed-point realization of the synchronization algorithm and introduce some simplifications to reduce, as much as possible, the cost in area of the circuit without losing its performance.