A low complexity joint equalizer and decoder for 1000Base-T Gigabit Ethernet

Author

Haratsch, Erich F. ; Azadet, Kamran

Author_Institution

DSP & VLSI Syst. Res., Lucent Technol. Bell Labs., Holmdel, NJ, USA

fYear

2000

fDate

2000

Firstpage

465

Lastpage

468

Abstract

A VLSI architecture for low complexity joint decoding and equalization for 1000Base-T Gigabit Ethernet is presented. A one-tap parallel decision-feedback decoder jointly decodes the trellis and cancels the ISI due to the first tap of the post-cursor channel impulse response. The one-dimensional branch metrics are precomputed in a look-ahead fashion to meet the speed requirements. The less significant tail of the channel impulse response is canceled with a simple decision-feedback prefilter. The design has been implemented in 3.3 V, 0.25 μm standard cell CMOS process for operation at 125 MHz

Keywords

CMOS digital integrated circuits; VLSI; application specific integrated circuits; decision feedback equalisers; decoding; digital signal processing chips; high-speed integrated circuits; interference suppression; intersymbol interference; local area networks; trellis coded modulation; 0.25 micron; 1000Base-T Gigabit Ethernet; 125 MHz; 3.3 V; ISI cancellation; TCM signals; VLSI architecture; decision-feedback prefilter; decoding; equalization; low complexity joint equalizer/decoder; one-dimensional branch metrics; one-tap parallel decision-feedback decoder; post-cursor channel impulse response; standard cell CMOS process; trellis codes; Application specific integrated circuits; Bit error rate; Crosstalk; Decision feedback equalizers; Decoding; Digital signal processing; Ethernet networks; USA Councils; Very large scale integration; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5809-0

Type

conf

DOI

10.1109/CICC.2000.852709

Filename

852709