Title :
Media processor core architecture for realtime, bi-directional MPEG4/H.26X codec with 30 fr/s for CIF-video
Author :
Kamemaru, T. ; Ohira, H. ; Suzuki, H. ; Asano, K. ; Yoshimoto, M. ; Murakami, T.
Author_Institution :
Inf. & Commun. Syst. Dev. Center, Mitsubishi Electr. Co. Ltd., Kamakura, Japan
Abstract :
We have developed a media processor core for MPEG4/H.26X codec LSI, which realizes a real-time bi-directional encoding/decoding for CIF-resolution video at the frame rate of 30 fr/s. The core processor contains 6.3 M-transistors on only 14 mm silicon area and consumes 280 mW at 1.8 V. It features an MPEG-oriented hybrid architecture which incorporates a SIMD processor optimized for matrix-operation, a programmable VLC engine and two-dimensional multifunction DMA. Another features are a memory reduction approach by hardware assist and an operand isolation scheme, which realizes low cost and low power characteristics, respectively
Keywords :
digital signal processing chips; low-power electronics; multimedia computing; parallel architectures; telecommunication standards; video codecs; 1.8 V; 280 mW; CIF-video; MPEG-oriented hybrid architecture; SIMD processor; bi-directional MPEG4/H.26X codec; frame rate; low power characteristics; matrix-operation; media processor core architecture; memory reduction approach; operand isolation scheme; programmable VLC engine; two-dimensional multifunction DMA; Bidirectional control; Codecs; Costs; Decoding; Encoding; Engines; Hardware; Large scale integration; MPEG 4 Standard; Silicon;
Conference_Titel :
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5809-0
DOI :
10.1109/CICC.2000.852711
