A 1.5 GHz Fully-Monolithic CMOS LNA and Its Noise Behavior

A 1.8 V, 1.57542 GHz LNA has been designed for a 0.5-¿m CMOS process. This amplifier provides a forward gain of 19 dB with a low noise figure of only 2 dB while drawing 17 mW DC power. Unlike most of the circuits in literature, this design includes on-chip biasing and matching networks. A noise rejection study on a single-ended and a differential LNA designed in the proposed approach shows that the differential amplifier is more noisy for the same gain while being less sensitive to common-mode noise.