Validation of an accurate and simple delay model and its application to voltage scaling

A simple, yet accurate, delay estimation model for submicron CMOS is validated by simulation and measurements on several test chips. The validity of the model is demonstrated for simple gates and full adders composed by various circuit techniques, and for complete digital filter designs. Furthermore, we show that the supply voltage in principle may be reduced as much as possible to reduce the power consumption, while the degraded performance may be compensated by utilizing parallel processing. Sensitivity analysis, simulation and test chip measurements indicate, however, that worst case conditions for the process and battery cell voltage, may limit the supply voltage reduction for practical reasons. The delay model may be used as a delay calculator, and as a mean to trade area against power consumption. Eventually, we suggest a simple, yet efficient, way to explore the initial design space for voltage scaled and multiple-V_DD designs, by combining the delay model and a standard gate level simulator