Architecture oriented logic optimization for lookup table based FPGAs

A logic optimization criterion for lookup-table based field programmable gate arrays (FPGAs) is presented. Based on this criterion, several key operations of logic optimization, such as extraction, decomposition, resubstitution and simplification, are discussed, so as to make them evaluate the circuit cost in accordance with the target technology. Using our approaches to do logic optimization for lookup-table based FPGAs, we obtain a good starting point for technology mapping. On the basis of 25 benchmark examples, our optimized circuits require 14% fewer configurable logic blocks (CLBs) than the circuits optimized by MIS-II if both are subsequently mapped using MIS-pga. Moreover, the number of circuit levels is also slightly improved