Title :
A locally-clocked dynamic logic serial/parallel multiplier
Author :
Hoyer, Gregg N. ; Sechen, Carl
Author_Institution :
Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
Abstract :
Locally-clocked (LC) dynamic logic is an asynchronous circuit technique that uses an event-driven controller to moderate a fine-grained pipeline consisting of latching dynamic logic gates. This paper extends the methodology to include feedback between successive pipeline stages. LC dynamic logic´s ability to handle feedback is illustrated with the design of a 660 MHz serial/parallel multiplier implemented in a 1 μm, 5 V CMOS process
Keywords :
CMOS logic circuits; asynchronous circuits; multiplying circuits; pipeline arithmetic; 1 micron; 5 V; 660 MHz; CMOS process; asynchronous circuit technique; event-driven controller; fine-grained pipeline; latching dynamic logic gates; locally-clocked dynamic logic serial/parallel multiplier; successive pipeline stages; CMOS logic circuits; CMOS process; Clocks; Delay; Feedback; Logic circuits; Logic design; Logic devices; Logic gates; Pipelines;
Conference_Titel :
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5809-0
DOI :
10.1109/CICC.2000.852713
