A low-power implantable neuroprocessor on nano-FPGA for Brain Machine interface applications

Author

Zhang, Fei ; Aghagolzadeh, Mehdi ; Oweiss, Karim

Author_Institution

Dept. of Electr. & Comput. Eng., Michigan State Univ., East Lansing, MI, USA

fYear

2011

fDate

22-27 May 2011

Firstpage

1593

Lastpage

1596

Abstract

This paper presents the implementation of a low-power and implantable neuroprocessor on low-cost nano-FPGA for data reduction and on-the-fly spike sorting in Brain Machine Interface applications. Detailed analysis of efficient utilization of the hardware resources, power consumption and design scalability are provided. The prototype we report here enables simultaneous processing of 32-channel data sampled at 25 kHz/channel with 8-bit/sample resolution with less than 5 mW power consumption for all modes of operation (monitoring, compression and sensing) at 1.2 V core voltage supply on a 5 mm × 5 mm nano-FPGA.

Keywords

biomedical electronics; brain-computer interfaces; field programmable gate arrays; low-power electronics; microprocessor chips; nanoelectronics; neural chips; neurophysiology; power aware computing; prosthetics; 32-channel data processing; brain machine interface application; data reduction; design scalability; low-power implantable neuroprocessor; nanoFPGA; spike sorting; voltage 1.2 V; Clocks; Discrete wavelet transforms; Feature extraction; Field programmable gate arrays; Power demand; Sorting; Wireless communication; Neuroprocessor; brain machine interfaces; compression; low-power; nano-FPGA; spike sorting;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech and Signal Processing (ICASSP), 2011 IEEE International Conference on

Conference_Location

Prague

ISSN

1520-6149

Print_ISBN

978-1-4577-0538-0

Electronic_ISBN

1520-6149

Type

conf

DOI

10.1109/ICASSP.2011.5946801

Filename

5946801