Title :
On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation
Author :
Qi, Xiaoning ; Wang, Gaofeng ; Yu, Zhiping ; Dutton, Robert W. ; Young, Tak ; Chang, Norman
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
Abstract :
On-chip inductance modeling of VLSI interconnects is presented which captures 3D geometry from layout design and process technology information. Analytical formulae are derived for quick and accurate inductance estimation which can be used in circuit simulations and whole chip extraction screening process. Circuit simulations show critical global wire inductive effects as well as power and ground inductive noise
Keywords :
VLSI; circuit layout CAD; circuit simulation; inductance; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; integrated circuit noise; 3D geometry; RLC extraction; VLSI interconnects; circuit simulation; critical global wire inductive effects; inductance estimation; inductive noise; layout design; on-chip inductance modeling; process technology information; whole chip extraction screening; Circuit noise; Circuit simulation; Data mining; Inductance; Information geometry; Integrated circuit interconnections; Process design; Solid modeling; Very large scale integration; Wire;
Conference_Titel :
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5809-0
DOI :
10.1109/CICC.2000.852714
