DocumentCode :
2160111
Title :
A superassociative tagged cache coherence directory
Author :
Lilja, David J. ; Ambalavanan, Shanthi
Author_Institution :
Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
fYear :
1994
fDate :
10-12 Oct 1994
Firstpage :
42
Lastpage :
45
Abstract :
Dynamically tagged directories are memory-efficient mechanisms for maintaining cache coherence in shared-memory multiprocessors. These directories use special-purpose caches of pointers that are subject to two types of overflow: (1) pointer overflow, which limits the maximum sharing of a memory block, and (2) set overflow, which forces the premature invalidation of cached blocks. We propose a superassociative tagged directory that can preserve some of the cached copies of a memory block when a set overflows by allowing multiple address tags in the same set to contain the same address value. Verilog descriptions are used to estimate its implementation cost and timing delay, and a multiprocessor cache simulator is used to evaluate its performance
Keywords :
buffer storage; coherence; delays; shared memory systems; storage management; Verilog descriptions; dynamically tagged directories; implementation cost estimation; maximum sharing; memory block; memory-efficient mechanisms; multiple address tags; multiprocessor cache simulator; performance evaluation; pointer overflow; premature invalidation; set overflow; shared-memory multiprocessors; special-purpose pointer caches; superassociative tagged cache coherence directory; timing delay; Computer science; Costs; Delay effects; Delay estimation; Hardware design languages; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-6565-3
Type :
conf
DOI :
10.1109/ICCD.1994.331851
Filename :
331851
Link To Document :
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