Low power bus coding techniques considering inter-wire capacitances

Author

Sotiriadis, Paul P. ; Chandrakasan, Anantha

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA

fYear

2000

fDate

2000

Firstpage

507

Lastpage

510

Abstract

The power dissipation associated with driving data buses can be significant, especially considering the increasing component of inter-wire capacitance. Previous work on bus encoding has focused on minimizing transitions to reduce power dissipation. In this paper, it is shown that transition reduction is not necessarily the best approach for reducing power when the effects of inter-wire capacitance are considered. An electrical model for data buses designed with submicron technologies is presented and a family of coding techniques is proposed that can reduce the average power consumption of the bus by 40%

Keywords

Capacitance; Digital integrated circuits; Encoding; Equivalent circuits; Integrated circuit modeling; Low-power electronics; Network analysis; System buses; average power consumption reduction; bus encoding; data bus driving; electrical model; inter-wire capacitances; low power bus coding techniques; power dissipation; submicron technologies; Driver circuits; Encoding; Energy consumption; Parasitic capacitance; Power dissipation; Power supplies; Recycling; Resistors; Signal to noise ratio; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5809-0

Type

conf

DOI

10.1109/CICC.2000.852719

Filename

852719