Title :
WiCkeD: analog circuit synthesis incorporating mismatch
Author :
Antreich, K. ; Eckmueller, J. ; Graeb, H. ; Pronath, M. ; Schenkel, E. ; Schwencker, R. ; Zizala, S.
Author_Institution :
Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
Abstract :
This paper presents a method to consider local process variations, which crucially influence the mismatch-sensitive analog components, within a new simulation-based analog synthesis tool called WiCkeD. WiCkeD includes tolerance analysis, performance optimization and design centering, and is a university tool used in industry for the design of analog CMOS circuits
Keywords :
CMOS analogue integrated circuits; analogue integrated circuits; circuit CAD; circuit optimisation; circuit simulation; integrated circuit design; tolerance analysis; WiCkeD; analog CMOS circuits; analog circuit synthesis; design centering; local process variations; mismatch-sensitive analog components; performance optimization; simulation-based analog synthesis tool; tolerance analysis; Analog circuits; Circuit synthesis; Circuit topology; Design automation; Design optimization; Electronic design automation and methodology; Mirrors; Monte Carlo methods; Robustness; Signal design;
Conference_Titel :
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5809-0
DOI :
10.1109/CICC.2000.852720
