Title :
A massively parallel multithreaded architecture: DAVRID
Author :
Ha, Sangho ; Kim, Junghwan ; Rho, Eunha ; Nah, Yoonhee ; Han, Sangyong ; Hwang, Daejoon ; Kim, Heunghwan ; Cho, Seungho
Author_Institution :
Dept. of Comput. Sci. & Stat., Seoul Nat. Univ., South Korea
Abstract :
MPAs (massively parallel architectures) should address two fundamental issues for scalability: synchronization and communication latency. Dataflow architectures cause problems of excessive synchronization costs and inefficient execution of sequential programs while they offer the ability to exploit massive parallelism inherent in programs. In contrast, MPAs based on the von Neumann computational model may suffer from inefficient synchronization mechanism and communication latencies. DAVRID (Dataflow von Neumann, RISC Hybrid) is a massively parallel multithreaded architecture. By combining the advantages of the von Neumann model and the dataflow model, DAVRID preserves good single thread performance and tolerates latency and synchronization costs. We describe the DAVRID architecture and evaluate it through simulation results over several benchmarks
Keywords :
instruction sets; parallel architectures; parallel processing; parallel programming; reduced instruction set computing; synchronisation; DAVRID; Dataflow von Neumann RISC Hybrid; MPAs; communication latency; dataflow architectures; massive parallelism; massively parallel multithreaded architecture; scalability; sequential programs; single thread performance; synchronization; von Neumann computational model; Computer architecture; Computer science; Contracts; Costs; Data engineering; Delay; Processor scheduling; Registers; Scalability; Yarn;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-6565-3
DOI :
10.1109/ICCD.1994.331857