Title :
Distributed reconfiguration of fault tolerant VLSI multipipeline arrays with constant interstage path lengths
Author :
Al-Asaad, Hussain ; Vai, Mankuan ; Feldman, James
Author_Institution :
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
Abstract :
A new fault tolerant multipipeline array architecture and its diagnosis/reconfiguration algorithm is presented. This multipipeline array design methodology is characterized by constant, fault distribution independent interstage path lengths. Other features include a low hardware overhead and a high survival rate when it is compared to existing approaches
Keywords :
VLSI; fault tolerant computing; pipeline processing; reconfigurable architectures; reliability; constant interstage path lengths; diagnosis/reconfiguration algorithm; distributed reconfiguration; fault distribution; fault tolerant VLSI multipipeline arrays; hardware overhead; multipipeline array architecture; multipipeline array design methodology; survival rate; Circuit faults; Design methodology; Fault tolerance; Flip-flops; Integrated circuit interconnections; Logic arrays; Multiprocessor interconnection networks; Pipelines; Switches; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-6565-3
DOI :
10.1109/ICCD.1994.331858
