Delay-verifiability of combinational circuits based on primitive faults

It is shown that verifying the timing of a circuit by testing may require tests which can detect the simultaneous presence of more than one path delay fault. We introduce a special class of path delay faults, called primitive faults, whose detection is shown to be necessary and sufficient to ensure the temporal correctness of a circuit. Using this result, we develop a synthesis procedure for combinational circuits that can be tested for correctness of timing. Experimental data show that such implementations usually require less area than completely delay testable implementations