SYNCBIST: SYNthesis for concurrent built-in self-testability

Author

Harris, Ian G. ; Orailoglu, A.

Author_Institution

Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA

fYear

1994

fDate

10-12 Oct 1994

Firstpage

101

Lastpage

104

Abstract

We present a system which synthesizes, from a behavioral description, an RTL circuit which is testable with a high degree of test concurrency. The system produces a datapath containing test registers, and a BIST test plan for the testing of the chip. All design decisions are made using an estimate of test conflicts, which is based on an analysis of the reachability of each component port from I/O pins and test registers. Chip testing according to the partial-intrusion BIST methodology is assumed. Empirical results show the effect of test conflicts on the test application time, and highlight the benefit of using the proposed synthesis approach for test conflict reduction

Keywords

VLSI; built-in self test; circuit CAD; design for testability; logic CAD; logic testing; BIST test plan; I/O pins; RTL circuit; SYNCBIST; behavioral description; component port; concurrent built-in self-testability; dataflow graphs; datapath; design decisions; partial-intrusion BIST methodology; reachability; test application time; test concurrency; test conflict reduction; test conflicts; test registers; Automatic testing; Built-in self-test; Circuit synthesis; Circuit testing; Concurrent computing; Hardware; Process design; Registers; Semiconductor device testing; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-6565-3

Type

conf

DOI

10.1109/ICCD.1994.331864

Filename

331864