VLSI implementation of a realtime wavelet video coder

Author

Omaki, Roberto Y. ; Dong, Yu ; Miki, Morgan H. ; Furuie, Makoto ; Yamada, Shohei ; Taki, Daisuke ; Tarui, Masaya ; Fujita, Gen ; Onoye, Takao ; Shirakawa, Isao

Author_Institution

Dept. of Inf. Syst. Eng., Osaka Univ., Japan

fYear

2000

fDate

2000

Firstpage

543

Lastpage

546

Abstract

The architecture of a realtime wavelet video coder is described, with the main emphasis put on memory bandwidth reduction and efficient VLSI implementation. The proposed architecture adopts a modified 2-D subband decomposition scheme, alongside of a parallelized pipelined Embedded Zerotree Wavelet coder architecture. The video encoder is integrated in a 0.35 μm 3LM chip by using 341 K transistors on a 4.93×4.93 mm² die, which can process 720×480 30 fps pictures in realtime

Keywords

CMOS digital integrated circuits; VLSI; digital signal processing chips; parallel architectures; pipeline processing; real-time systems; video coding; wavelet transforms; 0.35 micron; 3LM chip; CMOS IC; DSP chip; VLSI implementation; embedded zerotree wavelet coder architecture; memory bandwidth reduction; modified 2D subband decomposition scheme; parallelized pipelined coder architecture; realtime wavelet video coder; Bandwidth; Computer architecture; Discrete cosine transforms; Discrete wavelet transforms; Frequency; Information systems; Quantization; Systems engineering and theory; Very large scale integration; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5809-0

Type

conf

DOI

10.1109/CICC.2000.852726

Filename

852726