Title :
Design of TSC code-disjoint inverter-free PLA´s for separable unordered codes
Author :
Piestrak, Stanislaw J.
Author_Institution :
Inst. of Eng. Cybern., Tech. Univ. Wroclaw, Poland
Abstract :
This paper considers design of totally self-checking (TSC) code-disjoint (CD) PLA´s under fault model which covers three classes of typical PLA faults. The inputs of a PLA are encoded with a separable unordered code and any PLA is inverter-free, which guarantees that it is crosspoint-irredundant and no bridging fault may cause undetected errors. The new optimal separable unordered codes are constructed which, unlike most Berger and equivalent codes, are closed-a prerequisite for a TSC/CD realization of a PLA. A general procedure for designing a fast 2-stage PLA self-testing checker for any optimal separable unordered closed code is given. The design approach presented here can be readily used to design non-PLA circuits as well
Keywords :
circuit reliability; logic arrays; logic testing; PLA; PLA faults; TSC; code-disjoint; fault model; inverter-free; separable unordered codes; totally self-checking; Built-in self-test; Circuit faults; Cybernetics; Design engineering; Electrical fault detection; Electronic mail; Encoding; Fault detection; Logic devices; Programmable logic arrays;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-6565-3
DOI :
10.1109/ICCD.1994.331871
