Experimental evaluation of an active envelope load pull architecture for high speed device characterization

This paper presents a solution to the iterative nature of load pull characterization of transistor power performance. This has been achieved using a novel load pull architecture with a feedback loop at envelope frequencies within an active load pull system, which has been demonstrated and evaluated for single tone excitation. Furthermore employing the new architecture, a novel application is demonstrated which could be potentially useful in production environments, this is achieved using an amplitude modulated stimulus that reduces measurement time from hours to seconds.