Area and time limitations of FPGA-based virtual hardware

This paper examines the limitations of integrating programmable logic with a powerful core processor on the same die. An abstract model to investigate the area and delay of field programmable gate array architectures is presented. The model is used to show that a system implemented on FPGAs will require as much as 100 times more die area than its custom VLSI implementation and would be about 10 times slower. Our analysis shows that this high cost, inherent to the current FPGA-based architectures, is a severe limitation to virtual hardware development. A new approach to cell architecture and array organization is needed to deliver high computational speed-ups comparable to multiple processor systems with the same total die area