DocumentCode
2160768
Title
Optimum design for a two-stage CMOS I/O ESD protection circuit
Author
Li, Tong ; Bendix, P. ; Suh, D. ; Huh, Y.J. ; Rosenbaum, E. ; Kapoor, A. ; Kang, S.M.
Author_Institution
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Volume
2
fYear
1998
fDate
31 May-3 Jun 1998
Firstpage
113
Abstract
In industry, the design of CMOS ESD (electrostatic discharge) protection devices and circuits has been approached empirically. In this work, we propose an optimization methodology for a typical two-stage CMOS I/O protection circuit based on simulation. We have identified two kinds of design, namely resistor-limited and NMOS-limited, and demonstrated that the isolation resistor design is the key to the circuit´s protection level and performance
Keywords
CMOS analogue integrated circuits; circuit optimisation; electrostatic discharge; integrated circuit design; protection; resistors; CMOS; ESD protection circuit; NMOS-limited design; isolation resistor design; optimization methodology; resistor-limited design; two-stage I/O protection circuit; CMOS logic circuits; Circuit simulation; Driver circuits; Electrostatic discharge; Fingers; MOS devices; MOSFETs; Protection; Resistors; Thyristors;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location
Monterey, CA
Print_ISBN
0-7803-4455-3
Type
conf
DOI
10.1109/ISCAS.1998.706854
Filename
706854
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