A 70 nm gate length CMOS technology with 1.0 V operation

Author

Ono, A. ; Fukasaku, K. ; Matsuda, T. ; Fukai, T. ; Ikezawa, N. ; Imai, K. ; Horiuchi, T.

Author_Institution

ULSI Device Dev. Labs., NEC Corp., Kanagawa, Japan

fYear

2000

fDate

13-15 June 2000

Firstpage

14

Lastpage

15

Abstract

A 70-nm gate length CMOS technology for 1.0 V operation has been developed. This technology realizes high performance CMOS roadmap trend and utilizes sub-1 keV ion implantation for source/drain extension formations, quick-cooling RTA process, and ultra-thin gate dielectrics of 1.3 nm. The thickness of the gate dielectrics has been optimized in terms of both the I/sub ON/-I/sub OFF/, tradeoff and gate delay metrics. Obtained I/sub D//sup SAT/ for nMOS and pMOS are 723 /spl mu/A//spl mu/m (I/sub OFF/=16 nA//spl mu/m) and 290 /spl mu/A//spl mu/m (I/sub OFF/=20 nA//spl mu/m), respectively.

Keywords

CMOS integrated circuits; integrated circuit technology; ion implantation; low-power electronics; rapid thermal annealing; 1 keV; 1.0 V; 70 nm; CMOS technology; ion implantation; low voltage operation; rapid thermal annealing; ultrathin gate dielectric; Boron; CMOS technology; Degradation; Dielectrics; MOS devices; MOSFETs; National electric code; Silicon; Temperature dependence; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-6305-1

Type

conf

DOI

10.1109/VLSIT.2000.852750

Filename

852750