Title :
MISS tunnel diode: a capacitorless 4F/sup 2/ memory cell for sub-0.1 /spl mu/m era
Author :
Matsuoka, H. ; Sakata, T. ; Kimura, S.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
To develop a capacitorless 4F/sup 2/ memory cell (F: DRAM half pitch) for the sub-0.1 /spl mu/m era, we propose using the MISS tunnel diode, having a simple structure consisting of metal/insulator/p-type Si/n-type Si. We have demonstrated its feasibility for the first time by extensively studying its transport properties.
Keywords :
DRAM chips; MIS devices; tunnel diodes; 0.1 micron; DRAM; MISS tunnel diode; capacitorless 4F/sup 2/ memory cell; metal/insulator/p-type Si/n-type Si structure; transport properties; Capacitors; Current density; Diodes; Doping profiles; Electric variables; Ion implantation; Random access memory; Scalability; Temperature measurement; Voltage;
Conference_Titel :
VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6305-1
DOI :
10.1109/VLSIT.2000.852756
