Mass-productive high performance 0.5 /spl mu/m embedded FRAM technology with triple layer metal

Author

Itoh, A. ; Hikosaka, Y. ; Saito, T. ; Naganuma, H. ; Miyazawa, H. ; Ozaki, Y. ; Kato, Y. ; Mihara, S. ; Iwamoto, H. ; Mochizuki, S. ; Nakamura, M. ; Yamazaki, T.

Author_Institution

Fujitsu Labs. Ltd., Kanegasaki, Japan

fYear

2000

fDate

13-15 June 2000

Firstpage

32

Lastpage

33

Abstract

Mass-productive 0.5 /spl mu/m embedded FRAM with triple layer metal (one local interconnect and two Aluminum interconnects) has been developed. Fabrication processes are fully compatible with high-end logic LSIs using W-CVD via filling process. Using the high performance PZT capacitor and optimized metallization processes, we achieved high retention reliability even after triple layer metal process.

Keywords

ferroelectric storage; integrated circuit interconnections; integrated circuit metallisation; random-access storage; 0.5 micron; Al; PZT; PZT capacitor; PbZrO3TiO3; W; W-CVD via filling; aluminum interconnect; embedded FRAM technology; fabrication; local interconnect; mass production; multilevel metallization; reliability; triple layer metal process; Capacitors; Degradation; Fabrication; Ferroelectric films; Ferroelectric materials; Hysteresis; Metallization; Nonvolatile memory; Random access memory; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-6305-1

Type

conf

DOI

10.1109/VLSIT.2000.852757

Filename

852757