Characteristics of Al/sub 2/O/sub 3/ gate dielectric prepared by atomic layer deposition for giga scale CMOS DRAM devices

Author

Dae-Gyu Park ; Heung-Jae Cho ; Chan Lim ; In-Seok Yeo ; Jae-Sung Roh ; Chung-Tae Kim ; Jeong-Mo Hwang

Author_Institution

Memory R&D Div., Hyundai Electron. Ind. Co. Ltd., Ichon, South Korea

fYear

2000

fDate

13-15 June 2000

Firstpage

46

Lastpage

47

Abstract

This paper demonstrates characteristics of Al/sub 2/O/sub 3/ gate dielectric prepared by atomic layer deposition (ALD) for giga scale CMOS DRAM devices. Interface state density /spl sim/7/spl times/10/sup 10/ eV/sup -1/ cm/sup -2/ near the midgap and excellent reliability with a low gate leakage current were attained from Al/sub 2/O/sub 3//Si MOS system. p/nMOSFETs characteristics in terms of current drivability, transconductance (Gm), and subthreshold swing are described.

Keywords

CMOS memory circuits; DRAM chips; alumina; dielectric thin films; vacuum deposited coatings; Al/sub 2/O/sub 3/; Al/sub 2/O/sub 3/ gate dielectric; CMOS DRAM device; MOSFET; atomic layer deposition; current drivability; interface state density; leakage current; reliability; subthreshold swing; transconductance; Atomic layer deposition; Capacitance-voltage characteristics; Dielectric devices; Interface states; Leakage current; MOS capacitors; MOS devices; MOSFET circuits; Random access memory; Thermal degradation;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-6305-1

Type

conf

DOI

10.1109/VLSIT.2000.852763

Filename

852763