Circuit-level simulation and layout optimization for deep submicron EOS/ESD output protection device

Author

Li, Tong ; Ramaswamy, Sridhar ; Rosenbaum, Elyse ; Kang, Sung-Mo

Author_Institution

Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA

fYear

1997

fDate

5-8 May 1997

Firstpage

159

Lastpage

162

Abstract

This work presents circuit-level simulation and layout optimization techniques for a multifinger NMOS device. By considering the full thermal-coupling of heat sources at each drain finger, simulations reflect the device layout dependent behavior in silicon under EOS/ESD. Simulation reveals that each NMOS finger may carry a different stress current due to the non-symmetrical heat-coupling effect; as a result, the effective total NMOS width will be reduced. Simulation results agree well with the measured data. We also propose a design and layout optimization methodology which is illustrated with a design example

Keywords

CMOS integrated circuits; circuit analysis computing; circuit optimisation; electrostatic discharge; equivalent circuits; integrated circuit layout; integrated circuit modelling; protection; thermal analysis; EOS/ESD output protection device; NMOS drain finger; circuit-level simulation; deep submicron EOS/ESD protection; device layout dependent behaviour; heat sources; layout optimization; multifinger NMOS device; nonsymmetrical heat-coupling effect; stress current; thermal-coupling; CMOS technology; Circuit simulation; Computational modeling; Design optimization; Earth Observing System; Electrostatic discharge; Electrothermal effects; Fingers; MOS devices; Protection;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-3669-0

Type

conf

DOI

10.1109/CICC.1997.606605

Filename

606605