Title :
A parallel CMOS 2´s complement multiplier based on 5:3 counter
Author :
Guan, Z. ; Thomson, P. ; Almaini, A.E.A.
Author_Institution :
Dept. of Electr. & Electron. Eng., Napier Univ., UK
Abstract :
A parallel 8×8 2´s complement multiplier based on a novel 5:3 counter is presented. The structure of the multiplier is simple, regular, and very suitable for VLSI implementation. Compared with Wallace tree and Redundant Binary Addition Tree (N. Takagi et al., 1985), the proposed scheme requires less levels for the same number of partial products, resulting in a simpler and faster circuit
Keywords :
CMOS integrated circuits; VLSI; cellular arrays; digital arithmetic; parallel architectures; trees (mathematics); Redundant Binary Addition Tree; VLSI implementation; Wallace tree; faster circuit; parallel 8×8; parallel CMOS; twos complement multiplier; Adders; Application software; Arithmetic; Art; Binary trees; Counting circuits; Hardware; High performance computing; Integrated circuit interconnections; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-6565-3
DOI :
10.1109/ICCD.1994.331910
