DocumentCode
2161237
Title
A simple embedded DRAM process for 0.16-/spl mu/m CMOS technologies
Author
Liu, C.T. ; Diodato, P.W. ; Rogers, S. ; Lai, W.Y.C. ; Chen, C.J. ; Lloyd, E.J. ; Sun, C.Y. ; Barr, D. ; Liu, R. ; Chang, C.P. ; Trimble, L. ; Pai, C.S. ; Vaidya, H.
Author_Institution
Lucent Technol. Bell Labs., Murray Hill, NJ, USA
fYear
2000
fDate
13-15 June 2000
Firstpage
60
Lastpage
61
Abstract
A simple embedded DRAM (eDRAM) process that minimizes the front-end add-on cost is presented for 0.16-/spl mu/m CMOS technologies. The structure results in a low-leakage device (<20 fA/cell at 100/spl deg/C) suitable for future generations of eDRAMs. Without using poly-Si plugs or metal-0 bit-line runners, topography is identical to the core LOGIC process. Low-temperature MIM capacitors are easily integrated using the W-plugs of metal-2 level. The number of total additional lithographic steps is only 3-5.
Keywords
CMOS memory circuits; DRAM chips; integrated circuit technology; 0.16 micron; CMOS technology; LOGIC process; MIM capacitor; W plug; embedded DRAM; CMOS process; CMOS technology; Costs; FETs; Furnaces; Logic devices; MIM capacitors; Plugs; Random access memory; Surfaces;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-6305-1
Type
conf
DOI
10.1109/VLSIT.2000.852769
Filename
852769
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