A new asynchronous multiplier using Enable/Disable CMOS Differential Logic

Author

De Angel, Edwin ; Swartzlander, Earl, Jr. ; Abraham, Jacob

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

fYear

1994

fDate

10-12 Oct 1994

Firstpage

302

Lastpage

305

Abstract

This paper presents a technique for asynchronous logic design using ECDL (Enable/Disable CMOS Differential Logic). A pipelined serial-parallel multiplier clocked at 55.6 MHz has been designed to show the implementation of this technique. The serial-parallel multiplier architecture has been designed in ECDL using MAGIC, and circuit simulations have been done in HSPICE using a 2 μm model from MOSIS. An evaluation of the area using ECDL is presented and compared against techniques used in the past to show that a significant reduction in area overhead is possible

Keywords

CMOS integrated circuits; circuit analysis computing; circuit diagrams; digital simulation; logic design; multiplying circuits; sequential circuits; ECDL; Enable/Disable CMOS Differential Logic; HSPICE using; MAGIC; MOSIS; asynchronous logic design; asynchronous multiplier; circuit simulations; pipelined serial-parallel multiplier; serial-parallel multiplier architecture; Asynchronous circuits; CMOS logic circuits; Circuit simulation; Clocks; Computer architecture; Delay; Jacobian matrices; Logic design; Multivalued logic; Synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-6565-3

Type

conf

DOI

10.1109/ICCD.1994.331911

Filename

331911