A WSI macrocell fault circumvention strategy

Author

Swartzlander, Earl E., Jr.

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

fYear

1991

fDate

29-31 Jan 1991

Firstpage

90

Lastpage

96

Abstract

The use of a design paradigm that consists of a hierarchy of structures from cells to macrocells to functional elements to wafers greatly simplifies the design and development of wafer scale integration (WSI) systems. The authors examine the use of pooled spares, for fault circumvention at the macrocell level of the hierarchy. A method is provided that maximizes the yield of the pools of macrocells as a function of the yield of individual macrocells and the yield of the interconnection network. An example shows the application of this theory to a floating-point complex butterfly for signal processing applications

Keywords

VLSI; digital signal processing chips; fault tolerant computing; WSI macrocell; design paradigm; fault circumvention strategy; floating-point complex butterfly; interconnection network; pooled spares; signal processing applications; wafer scale integration; yield; Circuit faults; History; Integrated circuit interconnections; Logic; Macrocell networks; Multiprocessor interconnection networks; Read-write memory; Redundancy; Voting; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Wafer Scale Integration, 1991. Proceedings., [3rd] International Conference on

Conference_Location

San Francisco, CA

Print_ISBN

0-8186-9126-3

Type

conf

DOI

10.1109/ICWSI.1991.151701

Filename

151701