Microarchitectural synthesis of performance-constrained, low-power VLSI designs

New portable signal-processing applications such as mobile telephony, wireless computing, and personal digital assistants place stringent power consumption limits on their constituent components. Substantial power servings can be realized if 5 V designs are translated to use the new lower supply voltage standards. This conversion, however is not achieved easily: a design originally targeted for implementation in a 5 V technology will typically require significant re-work to meet timing and throughput requirements at the lower operating voltage. We describe a high-level synthesis system which assists the designer in performing this task, minimizing the need for manual re-design. Techniques employed in this work include pipelining and a new approach to module selection which minimizes power consumption subject to timing constraints. Using these and other high-level synthesis techniques to target designs to 3.3 V libraries, we show that it is possible to reduce power consumption by as much as 56% as compared to the original 5 V implementation, while meeting specified minimum throughput and maximum latency constraints