Transistor on capacitor (TOC) cell with quarter pitch layout for 0.13 /spl mu/m DRAMs and beyond

Author

Sato, M. ; Ishibashi, S. ; Kajiyama, T. ; Sakuma, M. ; Mizushima, I. ; Tsunashima, Y. ; Shoji, F. ; Yano, H. ; Nitayama, A. ; Hamamoto, T.

Author_Institution

Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan

fYear

2000

fDate

13-15 June 2000

Firstpage

82

Lastpage

83

Abstract

We present a new trench type cell, transistor on capacitor (TOC) cell with 1/4 pitch layout. Two kinds of new idea have been implemented. One is that the density of the trench capacitor is closest packed by introducing 1/4 pitch layout. The other is that the transfer transistor is fabricated over the trench capacitor by introducing the newly developed epitaxial growth and Chemical Mechanical Polish (CMP) technologies. As a result, trench opening can be enlarged without reducing the gate length of the transfer transistor.

Keywords

DRAM chips; capacitors; chemical mechanical polishing; epitaxial growth; 0.13 micron; DRAM; chemical mechanical polishing; epitaxial growth; quarter pitch layout; transfer transistor; transistor-on-capacitor cell; trench capacitor; Capacitance; Capacitors; Chemical technology; Crystallization; Epitaxial growth; Epitaxial layers; Fabrication; Planarization; Random access memory; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-6305-1

Type

conf

DOI

10.1109/VLSIT.2000.852778

Filename

852778