Architectural performance verification: PowerPC processors

Author

Surya, S. ; Bose, P. ; Abraham, J.A.

Author_Institution

IBM Corp., Austin, TX, USA

fYear

1994

fDate

10-12 Oct 1994

Firstpage

344

Lastpage

347

Abstract

We consider the problem of validating a functional (architectural) timing model coded to predict instructions-per-cycle (IPC) performance for an advanced superscalar processor family. We present a methodology based on loop test cases for validating such models. For the purpose of this paper, we focus on two key strategies within our overall validation methodology: transient mode testing; and steady-state parametric testing. We state a few key lemmas characterizing the underlying theory and present a set of experimental results to illustrate the use of these validation strategies

Keywords

formal verification; microcomputers; performance evaluation; reduced instruction set computing; PowerPC processors; RISC microprocessors; advanced superscalar processor family; architectural performance verification; architectural timing model; functional timing model; instructions-per-cycle performance; loop test cases; steady-state parametric testing; transient mode testing; validation methodology; Computational modeling; Dispatching; Hardware; Pipelines; Power engineering and energy; Power engineering computing; Predictive models; Reduced instruction set computing; Testing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-6565-3

Type

conf

DOI

10.1109/ICCD.1994.331922

Filename

331922