A novel digital symbol timing recovery implementation for high speed variable rate QPSK RF modems

An approach to symbol timing recovery is presented which uses a hybrid digital phase-locked loop. The implementation is presented along with a simple model for predicting loop behavior. The modulation removal, phase detector and loop filter are all digital whereas the VCXO uses analog components. The baseband eye diagram drives a digital phase detector to provide the timing phase error. This signal is independent of carrier phase information, thus permitting parallel symbol timing and carrier-phase-recovery operations