A sparse macromodeling method for RC interconnect multiports

Author

Liu, Ying ; Pileggi, Lawrence T. ; Strojwas, Andrzej J.

Author_Institution

Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

fYear

1997

fDate

5-8 May 1997

Firstpage

163

Lastpage

166

Abstract

This paper describes a technique for generating sparse RC interconnect macromodels. By inserting an artificial delay in the transconductance between distant port nodes, the technique can dramatically sparsify the time domain stencil of the N-port macromodel. The error introduced is measured in terms of the poles and residues of the RC circuit, thereby allowing accuracy vs. sparsity trade-offs to be made. Some examples are shown that demonstrate no noticeable loss of accuracy for significant improvements in sparsity

Keywords

RC circuits; circuit analysis computing; delays; digital integrated circuits; error analysis; integrated circuit interconnections; integrated circuit modelling; linear network analysis; multiport networks; sparse matrices; time-domain analysis; N-port macromodel; RC circuit; RC interconnect multiports; artificial delay; sparse macromodeling method; time domain stencil; transconductance; Application specific integrated circuits; Circuit simulation; Convolution; Current measurement; Frequency domain analysis; Integrated circuit interconnections; Piecewise linear approximation; Transconductance; Transfer functions; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-3669-0

Type

conf

DOI

10.1109/CICC.1997.606606

Filename

606606