A new test generation methodology using selective clocking for the clock line controlled circuits

This paper presents a novel sequential test generation technique for circuits with clock line control (CLC). CLC is a design for testability (DFT) technique that can transform a complex test generation problem into multiple small ones that are efficiently manageable by selectively enabling or disabling the synchronous operation of modules. The new test generation methodology for CLC circuits is smart enough to selectively clock modules, expand multiple time frames for a sequential module and compose these time frames to generate input and clock vectors for an entire circuit. Test generation for the ISCAS ´89 circuits, with and without both CLC and scan has been performed. High fault coverage in a short time has been achieved using test generator with CLC