Low temperature (<500/spl deg/C) SrTiO/sub 3/ capacitor process technology for embedded DRAM

Author

Nakahira, J. ; Kiyotoshi, M. ; Yamazaki, S. ; Nakabayashi, M. ; Niwa, S. ; Tsunoda, K. ; Lin, J. ; Shimada, A. ; Izuha, M. ; Aoyama, T. ; Tomita, H. ; Eguchi, K. ; Hieda, K.

Author_Institution

Technol. Dev. Div., Fujitsu Ltd., Japan

fYear

2000

fDate

13-15 June 2000

Firstpage

104

Lastpage

105

Abstract

We have developed low temperature SrTiO/sub 3/ (ST) capacitor process for embedded DRAM. ST film deposited at 475/spl deg/C was crystallized without additional annealing. 0.53nm SiO/sub 2/ equivalent thickness (teq) ST capacitor with Ru electrodes was obtained. The leakage current of the concave structure capacitor was less than 1fA/cell at /spl plusmn/0.8V for 256K 3-dimensional (3D) capacitors fabricated by the low temperature ST process. ST capacitor process can satisfy demands on lower processing temperature and scalability to very thin dielectric layer with low leakage current.

Keywords

DRAM chips; capacitors; leakage currents; strontium compounds; 475 C; SrTiO/sub 3/; SrTiO/sub 3/ capacitor; dielectric film; embedded DRAM; leakage current; low temperature process technology; Annealing; Binary search trees; Capacitors; Crystallization; Dielectric constant; Electrodes; Leakage current; Random access memory; Temperature; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-6305-1

Type

conf

DOI

10.1109/VLSIT.2000.852787

Filename

852787