DocumentCode
2161782
Title
Learning the optimal operating point for many-core systems with extended range voltage/frequency scaling
Author
Da-Cheng Juan ; Garg, Shelly ; Jinpyo Park ; Marculescu, Diana
Author_Institution
Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear
2013
fDate
Sept. 29 2013-Oct. 4 2013
Firstpage
1
Lastpage
10
Abstract
Near-Threshold Computing (NTC) has emerged as a solution that promises to significantly increase the energy efficiency of next-generation multi-core systems. This paper evaluates and analyzes the behavior of dynamic voltage and frequency scaling (DVFS) control algorithms for multi-core systems operating under near-threshold, nominal, or turbo-mode conditions. We adapt the model selection technique from machine learning to learn the relationship between performance and power. The theoretical results show that the resulting models satisfy convexity properties essential to efficiently determining optimal voltage/frequency operating points for minimizing energy consumption under throughput constraints or maximizing throughput under a given power budget. Our experimental results show that, compared with DVFS in the conventional operating range, extended range DVFS control including turbo-mode and near-threshold operation achieves an additional (1) 13.28% average energy reduction under isoperformance conditions, and (2) 7.54% average throughput increase under iso-power conditions.
Keywords
energy conservation; learning (artificial intelligence); multiprocessing systems; power aware computing; DVFS control algorithms; NTC; convexity properties; dynamic voltage and frequency scaling; energy efficiency; energy reduction; extended range voltage-frequency scaling; isoperformance conditions; isopower conditions; machine learning; many-core systems; model selection technique; near-threshold computing; near-threshold condition; next-generation multicore systems; nominal condition; turbo-mode condition; Accuracy; Adaptation models; Analytical models; Frequency measurement; Logic gates; Power demand; Throughput; Chip-multiprocessor; Convex optimization; Dynamic voltage and frequency scaling; Machine learning; Power management;
fLanguage
English
Publisher
ieee
Conference_Titel
Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2013 International Conference on
Conference_Location
Montreal, QC
Type
conf
DOI
10.1109/CODES-ISSS.2013.6658995
Filename
6658995
Link To Document