Title :
Single chip PCI bridge and memory controller for PowerPC microprocessors
Author :
Garcia, Michael J. ; Reynolds, Brian K.
Author_Institution :
Motorola Inc., Austin, TX, USA
Abstract :
The MPC105 is a highly integrated single chip design which provides a bridge between a variety of PowerPC microprocessors and the Peripheral Component Interconnect (PCI) bus. The MPC105 also integrates secondary cache control and a high performance memory controller which supports DRAM, SDRAM, and ROM. System designers will be able to design systems using peripherals already designed for PCI, providing an easy and cost effective bridge to PowerPC processors
Keywords :
DRAM chips; SRAM chips; microprocessor chips; peripheral interfaces; read-only storage; DRAM; MPC105; Peripheral Component Interconnect bus; PowerPC microprocessors; ROM; SDRAM; memory controller; secondary cache control; single chip PCI bridge; Bridges; Clocks; Costs; Decoding; Frequency; Microprocessors; Phase locked loops; Process design; Read only memory; Read-write memory;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-6565-3
DOI :
10.1109/ICCD.1994.331938
