Title :
A flash EEPROM cell with self-aligned trench transistor and isolation structure
Author :
Nakagawa, K. ; Yoshida, K. ; Masuda, S. ; Yoshino, A. ; Sakai, I.
Author_Institution :
ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan
Abstract :
For future high-density contactless-NOR-type flash EEPROMs, a new memory cell with self-aligned trench transistor and isolation structure has been proposed, and its feasibility was demonstrated. The short channel effect was suppressed markedly down to the feature size (F) of 0.14 /spl mu/m with the tunnel oxide thickness of 9 nm, and excellent endurance performance (>10/sup 5/ Fowler-Nordheim write/erase cycles) of the memory cell with the area of 0.16 /spl mu/m/sup 2/ (8F/sup 2/, F=0.14 /spl mu/m) was realized.
Keywords :
NOR circuits; flash memories; isolation technology; Fowler-Nordheim characteristics; high-density contactless NOR-type flash EEPROM; isolation structure; memory cell; self-aligned trench transistor; short channel effect; Annealing; Capacitors; Design for quality; EPROM; Fabrication; Paper technology; Space vector pulse width modulation; Threshold voltage; Virtual colonoscopy; Writing;
Conference_Titel :
VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6305-1
DOI :
10.1109/VLSIT.2000.852795