DocumentCode
2161993
Title
A Divide-by-4 circuit implemented in low voltage, high speed silicon bipolar topology
Author
Schuppener, G. ; Mokhtari, Mehrun ; Tenhunen, Hunnu
Author_Institution
Dept. of Electron., R. Inst. of Technol., Stockholm, Sweden
Volume
2
fYear
1998
fDate
31 May-3 Jun 1998
Firstpage
133
Abstract
This paper presents a Divide-by-4 circuit performing in the GHz range at very low supply voltage. Measurements have shown operation from 2.0-V and 2.2-GHz input frequency, down to 1.1-V and 1.2-GHz. The power consumption is approximately 2.5-mW/latch and 0.3-mW/latch, respectively. The circuit has been designed for nominal 1.5-V operation utilizing the bipolar part of Ericsson Component´s 0.6 μm BiCMOS technology (EPIC-3B)
Keywords
bipolar logic circuits; dividing circuits; 0.6 micron; 1.1 to 2.0 V; 1.2 to 2.2 GHz; BiCMOS technology; EPIC-3B; Ericsson Component; Si; divide-by-four circuit; low voltage high speed silicon bipolar topology; power consumption; BiCMOS integrated circuits; Circuit topology; Energy consumption; Frequency; Isolation technology; Latches; Logic; Low voltage; Resistors; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location
Monterey, CA
Print_ISBN
0-7803-4455-3
Type
conf
DOI
10.1109/ISCAS.1998.706859
Filename
706859
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