A triple gate oxide CMOS technology using fluorine implant for system-on-a-chip

Author

Goto, Y. ; Imai, K. ; Hasegawa, E. ; Ohashi, T. ; Kimizuka, N. ; Toda, T. ; Hamanaka, N. ; Horiuchi, T.

Author_Institution

ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan

fYear

2000

fDate

13-15 June 2000

Firstpage

148

Lastpage

149

Abstract

We have developed a triple gate oxide CMOS technology that integrates 0.10-/spl mu/m gate length 1.2-V high-speed CMOS (tox of 1.9 nm), low-power CMOS (tox of 2.5 nm) and 2.5-V I/O transistors (tox of 5.0 nm). The key technology is fluorine implantation in order to fabricate 1.9-nm and 2.5-nm gate oxide simultaneously. We selectively implanted fluorine into low-power CMOS area and successfully reduced the gate leakage current by 1.5 orders of magnitude.

Keywords

CMOS digital integrated circuits; high-speed integrated circuits; ion implantation; low-power electronics; oxidation; 0.1 micron; 1.2 V; I/O transistors; SiO/sub 2/:F; fluorine implantation; gate leakage current reduction; gate oxide fabrication; high-speed CMOS; hot carrier immunity; low-power CMOS; multiple IP cores; oxidation; selective implantation; subthreshold characteristics; system-LSI; system-on-a-chip; technology scaling; triple gate oxide CMOS technology; Argon; CMOS technology; Degradation; Dielectrics; Implants; Leakage current; MOS devices; System-on-a-chip; Tunneling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-6305-1

Type

conf

DOI

10.1109/VLSIT.2000.852804

Filename

852804