Title :
Architectural verification of processors using symbolic instruction graphs
Author :
Chandra, A.K. ; Iyengar, V.S. ; Jawalekar, R.V. ; Mullen, M.P. ; Nair, I. ; Rosen, B.K.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
High performance processor designs use techniques such as pipelining, multiple execution units, register renaming, bypass paths, and branch prediction to meet their goals. These techniques make them susceptible to design errors that are triggered only when executing complex sequences of instructions. We introduce a language called SIGL for specifying symbolic instruction graphs (SIGs) that can be used as templates for such test cases. SIGL allows specification of constraints in a high level template from which many test cases can be generated, all targeting some specific characteristic of a processor design. SIGL has been used successfully to check the conformance of various industrial processor designs to their architectural specifications
Keywords :
computer architecture; conformance testing; formal specification; graph theory; performance evaluation; specification languages; SIG; SIGL; architectural specifications; architectural verification; branch prediction; bypass paths; design errors; high level template; high performance processor designs; industrial processor designs; multiple execution units; pipelining; processor design; processor verification; register renaming; symbolic instruction graphs; Character generation; Counting circuits; Engines; Pipeline processing; Process design; Registers; Resource management; State-space methods; System testing; User interfaces;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-6565-3
DOI :
10.1109/ICCD.1994.331949
