A parallel method for functional verification of medium and high throughput DSP synthesis

Functional verification of large digital synchronous circuits with respect to complex arithmetic and decision making algorithms is becoming more and more important. Indeed, today, system complexities are still growing, while time-to-marked is still decreasing. First-time-right circuits can be obtained by adequate checking tools for timing, electrical and behavioural verification. The paper presents new results for automatic functional verification, based on the SFG-tracing methodology, applied on applications for medium and high throughput DSP, such as audio, video and image processing. The verification is formal, complete, efficient and independent. It checks functional correctness across synthesis tasks such as allocation, scheduling, clustering, specific datapaths and controller generation, redundancy removal, buffering, pipelining, retiming, etc